The present invention generally relates to a method for manufacturing semiconductor devices, and more particularly, to a method for forming a protrusive alignment-mark in semiconductor devices.
With the rapid developments of semiconductor industry, the dimensions of integrated circuits (ICs) are largely scaled down into sub-micron level such that photolithography techniques therefore play an important role in semiconductor process, particularly, such as an alignment-mark for calibration. Usually, the alignment is exactly used for the adjustment of wafer orientation. While the position of the alignment-mark may be incorrect or indefinite during semiconductor process, the alignment-mark can not be a reference coordinates of an alignment so that the later processes, even yield rate, are severely influenced. Mostly, an alignment-mark, traditionally groove patterns, is formed by etching to be on some unused regions of wafer.
Additionally, during a process of multilevel interconnects, an alignment procedure is served as an alignment between layers wherein a specific area of a layer is settled with an alignment-mark. The alignment device using alignment-mark among layers is named as a stepper. In the alignment interval, the stepper may automatically adjusts the wafer orientation into correct position by using the alignment-mark as a reference coordinates such that each of layer is accurately aligned to others. When adjusting the wafer position, the stepper emits some specific wavelengths of light through layers, generating interference waves and being transferred into electronic signal, to determine whether the layers is correctly aligned or not. The conventional process, which comprising alignment area and element area, to fabricate a recess alignment-mark is shown in FIGS. 1-6.
Referring to FIG. 1, a recess alignment-mark 12 having a width of 8 xcexcm, and a depth of 0.12 xcexcm, is conventionally etched on an alignment area 14 inside a substrate 10.
Referring to FIG. 2, a borophosphosilicate (BPSG) layer is formed on the recess alignment-mark 12 and the element area 16.
Referring to FIG. 3, an etching process is carried out to remove the borophosphosilicate (BPSG) layer on the recess alignment-mark 12 and the element area 16, and then a contact hole 30 is formed on the element area 16.
Referring to FIG. 4, a tungsten layer deposited on the recess alignment-mark 12 and the element area 16 has a thickness of 4000 angstroms and a step height 42.
Referring to FIG. 5, the element area 16 is planarized by a chemical-mechanical polishing (CMP). When the tungsten layer on the element area 16 is removed totally and thus a tungsten plug is simultaneously formed thereof. Finally, referring FIG. 6, the aluminum layer 60 is deposited on the recess alignment-mark 12 and the element area 16.
In accordance with the foregoing, the conventional recess alignment-mark 12 is etched on the substrate 10, but the depth of the recess alignment-mark 12 can""t adequately generate the interference weaves for alignment detection since the depth of the recess alignment-mark 12 is too shallow, merely 0.10 xcexcm or the less. Further, if a protrusive alignment-mark is formed by an etching step, thereby a great thickness of dielectric layer must be deposited before the formation of the protrusive alignment-mark. However, the thickness range of alignment area 14 is too small, therefore, a large portion of dielectric layer needs to be etched away resulting in a waste of manufacturing cost. As a result, an etching step on the substrate is quite improper for forming a recess alignment-mark 12.
Furthermore, in the period of CMP process, a portion of recess alignment-mark 12 will be vanished so that a zero step height 42a is formed on element area. In other words, a wavelength difference can""t be detected leading to alignment failure of wafer or dies.
Consequently, the conventional recess alignment-mark 12 formed by etching is not able to an adequate depth of recess alignment-mark 12 so that the recess alignment-mark 12 having a zero step height 42a, which cause the alignment failure in lithography, after the CMP process.
In view of the problems encountered with the foregoing conventional alignment-mark wherein these problems includes the insufficient of etching depth and the disappearance of step height with respect to the alignment-mark.
As a result, the primary object of the present invention is to provide a method of forming a protrusive alignment-mark having a step height for signal detection.
Another object of the present invention is to determine a fitting thickness of the protrusive alignment-mark by precisely control the thickness of the photoresist layer.
Still another object of the present invention is that the photoresist layer can be removed away to prevent the element area from contaminant after forming the protrusive alignment-mark.
According to the above objects, the present invention sets forth a method of forming a protrusive alignment-mark. A photolithography process is performed to form a patterned photoresist layer on a substrate wherein the substrate has an element region and an alignment region, and the patterned photoresist layer has an element photoresist-patterned region and an alignment photoresist-patterned region. Afterwards, a first dielectric layer is deposited on the element photoresist-patterned region and the alignment photoresist-patterned region. The excess portion of first dielectric layer above the patterned photoresist layer is removed such that the patterned photoresist layer is coplanar with the first dielectric layer and thus the patterned photoresist layer is exposed. The patterned photoresist layer on the element region and said alignment region is stripped to form a protrusive alignment-mark on the alignment region.
Thereafter, a second dielectric layer is formed on the protrusive alignment-mark and element region, and thereby retaining a step height of the protrusive alignment-mark. An etching process with respect to the element region and the alignment region is employed to remove the second dielectric layer on the protrusive alignment-mark, and etching a contact hole on the element region. A first conductive layer is formed on the protrusive alignment-mark and the element region. A planarization process is employed to planarize the element region to retain the step height of the protrusive alignment-mark all the time. A second conductive layer is formed on the protrusive alignment-mark and the element region for multilevel interconnects.
In summary, the present invention is to provide a method of forming a protrusive alignment-mark having a step height for signal detection after a CMP process. Additionally, the protrusive alignment-mark is suitable for mask ROM, DRAM, flash RAM and logic elements in the alignment procedure of semiconductor process. Most importantly, the thickness of protrusive alignment-mark is constructed by controlling the thickness of photoresist layer.